<!– SPDX-FileCopyrightText: 2026 Ahmed Imamović SPDX-FileCopyrightText: 2026 Tarik Hamedović SPDX-License-Identifier: CC-BY-SA-4.0 –>

uberclock_core

This module wires the Verilog UberClock core into the LiteX SoC and exposes its control, interrupt, and capture interfaces.

uberclock_core.py

Use-case

This file integrates the Verilog top-level uberclock DSP core into a LiteX SoC.

It does four things:

  1. Adds all required RTL sources (.v + .mem) to the LiteX build.

  2. Exposes the UberClock configuration surface as CSRs in the SYS clock domain.

  3. Transfers configuration snapshots atomically SYS->UC via an Async FIFO (so the UC domain sees stable/consistent configuration updates).

  4. Bridges UC->SYS events/data: - ce_down pulse becomes a LiteX interrupt (EventManager) in SYS. - optional low-speed capture readback returns to SYS CSRs - optional high-speed capture sample is wired into UberDDR3 (if present)

Expected SoC conventions

  • SoC provides clock domains:

    • sys : CPU/CSR domain

    • uc : UberClock domain (e.g. exact 65 MHz)

  • The platform defines IOs:

    • adc_clk_ch0/1, adc_data_ch0/1

    • da1_clk/da1_wrt/da1_data and da2_clk/da2_wrt/da2_data

    • user_led (or you pass a Cat(…) of pads via leds)

  • uberclock.v matches the port names wired in ports below.

Notes

  • CSRConfigAFIFO produces UC-domain signals named out_<field>_uc. This module simply maps those to the Verilog instance inputs.

  • All logic and signal wiring is unchanged from your current implementation; this is a readability + correctness refactor (e.g. platform defined, consistent naming).

uberclock_soc.uberclock_core.add_uberclock_fullrate(soc, leds)[source]

Integrate UberClock into the SoC (UC domain).

Parameters:

  • soc – LiteX SoC instance (must have platform, irq, add_csr, and clock domains).

  • leds – A Cat(…) of LED pads (or any signal vector) used for optional activity indicator.

  • effects (Side)

  • ------------

  • sources (- Adds RTL)

  • CSRs (- Adds) –

    • main : UberClock configuration & capture controls

    • evm : interrupt source (ce_down)

    • cfg_link : CSR snapshot commit FIFO

  • module. (- Instantiates the Verilog uberclock)

  • exists. (- Optionally wires high-speed capture into soc.ubddr3 if it)