<!– SPDX-FileCopyrightText: 2026 Ahmed Imamović SPDX-FileCopyrightText: 2026 Tarik Hamedović SPDX-License-Identifier: CC-BY-SA-4.0 –>

rtl_sources

This module resolves repository layout and adds Verilog sources to the LiteX platform.

class uberclock_soc.rtl_sources.RtlLayout(repo_root: Path)

Bases: object

Resolved source layout for this repo.

repo_root: Path

uberclock_soc.rtl_sources.rtl_layout() → RtlLayout

Return detected source layout rooted at the repository root.

uberclock_soc.rtl_sources.rtl_dir() → Path

Compatibility accessor for the repository root used by add_sources().

uberclock_soc.rtl_sources.add_sources(platform, rel_files: Iterable[str], base_dir: Path | None = None) → None

Add RTL files to a LiteX platform.

rel_files are paths relative to base_dir (default: repository root). Missing files raise FileNotFoundError with a helpful list.