<!--
SPDX-FileCopyrightText: 2026 Ahmed Imamović
SPDX-FileCopyrightText: 2026 Tarik Hamedović
SPDX-License-Identifier: CC-BY-SA-4.0
-->

rtl_sources
===========

This module resolves repository layout and adds Verilog sources to the LiteX
platform.

.. automodule:: uberclock_soc.rtl_sources
   :members:
   :undoc-members:
   :show-inheritance: