<!– SPDX-FileCopyrightText: 2026 Ahmed Imamović SPDX-FileCopyrightText: 2026 Tarik Hamedović SPDX-License-Identifier: CC-BY-SA-4.0 –>

streams

This module contains the UC-domain stream generators and packers used by the UberDDR3 capture path.

class uberclock_soc.streams.RampSource(*args: Any, **kwargs: Any)[source]

Bases: LiteXModule

Generates a 16-bit-lane ramp packed into bus_data_width-bit beats.

Packing:

  • Beat width: bus_data_width bits

  • Lanes: LANES = bus_data_width / 16

  • Lane i contains: (base_step + i) as a 16-bit value

  • base_step increments by LANES per accepted beat

class uberclock_soc.streams.SamplePackerStream(*args: Any, **kwargs: Any)[source]

Bases: LiteXModule

Samples one value per UC cycle, packs 16-bit samples into bus_data_width beats.

Packing:

  • Each UC cycle produces one 16-bit sample (sign-extended from sample_width)

  • LANES = bus_data_width / 16 samples are packed into one beat

  • The first sample goes to lane 0 (bits [15:0]), then lane 1, …, lane LANES-1

  • After LANES cycles, one beat is enqueued into the beat FIFO

Output:

  • Beat FIFO drains using valid/ready

  • frames is the number of beats to capture/emit (one beat = LANES samples)

  • overflow=1 means the beat FIFO could not accept completed beats in time

class uberclock_soc.streams.UCStreamMux(*args: Any, **kwargs: Any)[source]

Bases: LiteXModule

Selects between:

  • RampSource (internal test pattern)

  • External beat stream (typically SamplePackerStream)

Control:

  • start: starts ramp transfer when use_external=0

  • use_external: 0=ramp, 1=external stream

  • ramp_length_beats: ramp length in beats