<!– SPDX-FileCopyrightText: 2026 Ahmed Imamović SPDX-FileCopyrightText: 2026 Tarik Hamedović SPDX-License-Identifier: CC-BY-SA-4.0 –>
Project Overview
Clocks can be extracted from GPS satellite signals, or locally generated with MEMS oscillators, SAW resonators, quartz crystal (XTAL, XO) or piezo resonators, often set in ovens (TCXO, OCXO), derived from atomic properties (like Cesium Beam, Hydrogen Maser, Rubidium, Strontium or Ytterbium), or obtained in another way.
They differ in absolute accuracy, long-term frequency stability, short-term frequency stability, phase noise, physical size, complexity, immunity to external interference, power consumption, cost, and other characteristics. These differences are categorized as clock strata, whereby a clock source must meet a standardized set of requirements for each stratum level.
This work is about researching and exploiting the properties of multi-mode crystal oscillators in order to achieve stability comparable to a Stratum 2 Rubidium clock, all at a fraction of the total cost of ownership. The project focuses on collecting large empirical datasets, constructing experimental prototypes, and using DSP and numerical methods to mitigate:
temperature variations,
dynamic acceleration,
static gravity effects.
The goal is to improve XTAL frequency stability by means of mathematical and signal-processing methods implemented on FPGA, using open-source tools and a heterogeneous hardware/software architecture.
This is a Proof-of-Concept (PoC) and a stepping stone for future applied research projects on this theme, possibly extending into the field of Artificial Intelligence. In addition to a working prototype consisting of PCBs, FPGA gateware, and embedded firmware, the project is intended to deliver a series of scientific papers. :contentReference[oaicite:0]{index=0}
References
Papers are stored in
0.doc/Quartz/papersin the repository.
Hardware Platform
Physics Package: full-custom analog board with multi-mode quartz crystal
Hardware Architecture
The hardware architecture combines an analog physics package with a digital signal-processing and control platform.
At a high level, the system consists of:
a custom analog board containing the multi-mode quartz crystal and associated front-end circuitry,
an FPGA-based digital platform built around the AX7203,
dual ADC and DAC mezzanine modules for high-speed data acquisition and signal generation,
a LiteX-based SoC with a VexRiscV CPU for runtime control,
FPGA DSP blocks implementing conversion, routing, filtering, and analysis.
Conceptually, the signal path is:
Physics Package / Crystal
↓
ADC
↓
DSP on FPGA
↓
DAC
↓
measurement / debug / analysis
The digital part of the system is further divided into:
reusable DSP RTL under DSP Blocks,
SoC-side hardware integration under SoC Integration with LiteX,
firmware and runtime control under Firmware,
Python/LiteX integration and generated interfaces under Python Integration and API,
capture and analysis workflows under Examples.
This split keeps the reusable signal-processing blocks separate from the project-specific SoC integration and software control layers.
Work Packages
This section organizes the project into logical work packages and links each activity to the relevant implementation and documentation in the repository.
WP1: Acquisition of Hardware Platform
This work package covers the development and acquisition of the physical hardware platform.
Status:
✓ Design, manufacture, and debug the Physics Package card.
✓ Procure and distribute FPGA, ADC, and DAC cards.
Relevant documentation:
Hardware platform and project context: this page
SoC-side hardware context: SoC Integration with LiteX
WP2: Digital Infrastructure
This work package establishes the digital foundation of the system.
Status:
✓ Familiarize with ALINX boards.
✓ Toggle LEDs.
✓ Write RTL for interfaces to ADC and DAC chips.
✓ Write RTL to test their operation.
✓ Perform testing, debug, and fix problems as they arise.
✓ Create CPU hardware subsystem based on an open-source RISC-V core, memories, UART, and debug port.
✓ Create a bare-metal software skeleton as the foundation for future DSP applications, then create and test the software build flow.
✓ Test operation of CPU subsystem and profile its performance.
✓ Map ADCs and DACs into CPU memory space and test software communication with them.
Relevant documentation:
DSP RTL blocks: DSP RTL Blocks
ADC / DAC conversion path: AD/DA Conversion
SoC overview: SoC Integration with LiteX
Firmware code layout: Code Layout
Python/LiteX SoC integration: Overview
WP3: DSP Model and Documentation
This work package focuses on theoretical modeling and documentation of the DSP chain and crystal behavior.
Status:
☐ Model quartz crystal and DSP datapath in C or Python.
☐ Create a Theory of Operation document with explanation of concepts, tradeoffs, and criteria used to devise solutions.
☐ Post the Executive Summary here.
Relevant documentation:
DSP overview: DSP Blocks
CORDIC / downconversion path: CORDIC-Based Downconversion
Python SoC/user guide: Overview
WP4: Integration and Characterization
This work package brings together the analog and digital subsystems and focuses on measurement and characterization.
Status:
✓ Bring up the complete system with digital and analog card connected to each other.
✓ Perform manual characterization of individual crystals.
✓ Develop a semi- or fully-automated crystal characterization procedure.
Relevant documentation:
Low-speed capture workflow: Low-Speed Capture (CSR-Based)
High-speed capture workflow: High-Speed Capture (DDR3 + DMA)
UDP export workflow: Export DDR3 Data over UDP
Tracking algorithm: Tracking Algorithm
Measurement and crystal model: Characterization
WP5: Implementation of DSP Algorithms
This work package implements the DSP algorithms across hardware and software.
Status:
✓ Implement the hardware side of the DSP algorithm on FPGA.
☐ Implement the software side of the DSP algorithm in the RISC-V CPU.
☐ Integrate DSP hardware and software into a complete system.
Relevant documentation:
DSP RTL blocks: DSP RTL Blocks
Firmware C API: C / RTL API Reference
SoC integration: SoC Integration with LiteX
SoC API/reference: API Reference
WP6: Benchmarking
This work package evaluates system performance and validates the design.
Status:
☐ Test the DSP together with crystal.
☐ Fine-tune the DSP algorithm based on the obtained measurements.
☐ Conduct additional experiments with the corrected DSP algorithm in simulation and on hardware.
Additional requirements noted in the project plan:
A reliable reference clock source is needed, preferably Stratum 0.
A good spectrum analyzer is needed.
Relevant documentation:
High-speed capture workflow: High-Speed Capture (DDR3 + DMA)
UDP export and host-side analysis: Export DDR3 Data over UDP
Tracking workflow: Tracking Algorithm
WP7: Port from Vivado to openXC7
This work package focuses on toolchain portability and open-source FPGA flows.
Status:
☐ Port from Vivado to openXC7.
Relevant documentation:
SoC build flow: SoC Build and Host Tools
Documentation build flow: Build the Documentation
SoC overview: SoC Integration with LiteX
Project Status Summary
Conceptually, the work packages define the following development path:
Hardware
↓
RTL and DSP blocks
↓
SoC integration
↓
Firmware control
↓
Capture and export
↓
Analysis and benchmarking
Acknowledgements
We are grateful to NLnet Foundation for their sponsorship of this development activity.
This project was funded through the NGI0 Commons Fund, a fund established by NLnet with financial support from the European Commission’s Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No. 101135429. Additional funding is made available by the Swiss State Secretariat for Education, Research and Innovation.