uberClock Project Overview
Clocks can be extracted from GPS satellite signals, or locally generated with MEMS oscillators, SAW resonators, quartz crystal (XTAL, XO) or piezo resonators, often set in ovens (TCXO, OCXO), derived from atomic properties (like Cesium Beam, Hydrogen Maser, Rubidium, Strontium or Ytterbium), or obtained in another way.
They differ in absolute accuracy, long-term frequency stability, short-term frequency stability, phase noise, physical size, complexity, immunity to external interference, power consumption, cost, and other characteristics. These differences are categorized as clock strata, whereby a clock source must meet a standardized set of requirements for each stratum level.
This work is about researching and exploiting the properties of multi-mode crystal oscillators in order to achieve stability comparable to a Stratum 2 Rubidium clock, all at a fraction of the total cost of ownership. We plan on collecting large empirical datasets, constructing experimental prototypes, and using DSP / numerical methods to mitigate (1) temperature variations, (2) dynamic acceleration and (3) static gravity effects. The project aims for XTAL frequency stability by means of numerous mathematical calculations performed in FPGA, using open-source tools, including CflexHDL+PipelineC HLS flow.
This is a Proof-of-Concept (PoC) and stepping stone for future applied research projects on this theme, possibly extending into the field of Artificial Intelligence. In addition to a working prototype (PCBs, FPGA gateware and embedded firmware), the project will deliver a series of scientific papers.
References
Papers are stored in
0.doc/Quartz/papersin the repository.
Hardware Platform
Physics Package: full-custom analog board with multi-mode quartz crystal
Project Status
Acquisition of Hardware Platform
[x] Design, manufacture and debug the Physics Package card.
[x] Procure and distribute FPGA, ADC and DAC cards.
Digital Infrastructure
[x] Familiarize with ALINX boards.
Toggle LEDs.
Write RTL for interfaces to ADC and DAC chips.
Write RTL to test their operation.
Perform testing, debug, and fix the problems as they arise.
[x] Create CPU hardware subsystem based on an open-source RISC-V core, memories, UART and debug port.
[ ] Create a bare-metal software skeleton as the foundation for writing future DSP applications, then create and test the software build flow.
[ ] Test operation of CPU subsystem and profile its performance.
[ ] Map ADCs and DACs into CPU memory space and test software communication with them.
DSP Model and Documentation
[ ] Model quartz crystal and DSP datapath in C or Python.
[ ] Create a Theory of Operation document with explanation of concepts, tradeoffs and criteria used to devise solutions.
[ ] Post the Executive Summary here.
Integration and Characterization
[ ] Bring up the complete system with digital and analog card connected to each other.
[ ] Perform manual characterization of individual crystals.
[ ] Develop a semi- or fully-automated crystal characterization procedure.
Implementation of DSP Algorithms
[ ] Implement the hardware side of the DSP algorithm on FPGA.
[ ] Implement the software side of the DSP algorithm in the RISC-V CPU.
[ ] Integrate DSP hardware and software into a complete system.
Benchmarking
[ ] Test the DSP together with crystal.
A reliable reference clock source is needed, preferably Stratum 0.
A good spectrum analyzer is needed.
[ ] Fine-tune the DSP algorithm based on the obtained measurements.
[ ] Conduct additional experiments with the corrected DSP algorithm in simulation and on hardware.
Port from Vivado to openXC7
[ ] Port from Vivado to openXC7.
DSP Theory of Operation
WIP
Bit-Accurate Models
Multi-mode Quartz Crystal
WIP
DSP Datapath
WIP
Bit-Accurate Simulation of the Entire Algorithm
WIP
Hardware Architecture
WIP
Software Architecture
WIP
Acknowledgements
We are grateful to NLnet Foundation for their sponsorship of this development activity.