<!– SPDX-FileCopyrightText: 2026 Ahmed Imamović SPDX-FileCopyrightText: 2026 Tarik Hamedović SPDX-License-Identifier: CC-BY-SA-4.0 –>
DSP Blocks
This section documents the DSP Verilog modules under 1.dsp/rtl used in the
uberClock design. It starts with a general overview, then goes deeper into the
implementation of the specific modules.