<!– SPDX-FileCopyrightText: 2026 Ahmed Imamović SPDX-FileCopyrightText: 2026 Tarik Hamedović SPDX-License-Identifier: CC-BY-SA-4.0 –>

DSP RTL Blocks

The DSP RTL used in this design resides under 1.dsp/rtl. This section documents the reusable RTL modules that form the core signal processing path.

At a high level, the reusable DSP RTL is composed of:

• ADC interface blocks

• CORDIC and polar conversion blocks

• decimation and interpolation filters

• DAC interface blocks

The active SoC integrates these modules in 2.soc/1.hw/uberclock, where they are connected through CSR-controlled routing, buffering, and capture logic.

Contents

• ADC
  • adc/adc.v
• DAC
  • dac/dac.v
• Filters
  • Overview
  • Modules
  • Role in the datapath
  • Structure summary
• CORDIC
  • Overview
  • cordic.v
  • cordic_logic.v
  • cordic_pipeline_stage.v
  • cordic_pre_rotate.v
  • cordic_round.v
  • gain_and_saturate.v
  • cordic_top.v
  • Role in the datapath
  • Structure summary
• CORDIC16
  • Overview
  • cordic16.v
  • cordic_pipeline_stage.v
  • cordic_pre_rotate_16.v
  • cordic_round.v
  • gain_and_saturate.v
  • Role in the datapath
  • Structure summary
• Polar Conversion
  • to_polar/to_polar.v
  • Overview
  • Role in the datapath
  • Structure summary
• Placement Guidelines
  • Included in 1.dsp/rtl
  • Excluded from 1.dsp/rtl