<!– SPDX-FileCopyrightText: 2026 Ahmed Imamović SPDX-FileCopyrightText: 2026 Tarik Hamedović SPDX-License-Identifier: CC-BY-SA-4.0 –>

Python Integration and API

Note

This page collects the Python-facing part of the SoC: the packaged LiteX integration modules under src/uberclock_soc and the generated API documentation for them.

The Python package exists to do three jobs cleanly:

• assemble the AX7203 SoC without keeping all LiteX integration in one target file,

• wrap custom RTL blocks such as UberClock and UberDDR3 in reusable Python modules,

• document the software-visible control surface, capture flow, and module API.

If you are new to this tree, start from the parent SoC Platform section first. This page focuses on the Python implementation layer and the generated API reference.

Package Structure

• Overview
  • Why this package exists
  • Package map
  • High-level system composition
  • Typical use cases
  • Where the docs fit
• Architecture
  • Top-level build structure
  • Clock domains
  • Control path
  • Data path (capture)
  • Memory architecture
  • Interrupt and observability path
  • Module dependency view

Python API

• API Reference
  • uberclock_soc
  • clocking
  • csr_snapshot_fifo
  • rtl_filelist
  • rtl_sources
  • soc
  • streams
  • ubddr3
  • uberclock_core
  • uberclock_csrs
  • wishbone