<!– SPDX-FileCopyrightText: 2026 Ahmed Imamović SPDX-FileCopyrightText: 2026 Tarik Hamedović SPDX-License-Identifier: CC-BY-SA-4.0 –>

ubddr3

This module integrates the custom DDR3 controller, CPU access path, and DMA capture stream path.

class uberclock_soc.ubddr3.UberDDR3(*args: Any, **kwargs: Any)[source]

Bases: LiteXModule

UberDDR3 top-level integration block.

Use-case

This module wires a Verilog DDR3 controller (ddr3_top) into a LiteX SoC and provides two ways to write/read DDR.

CPU / software access (SYS domain):

  • Classic 32-bit Wishbone (LiteX standard) exposed as self.wb.

  • Width-converted up to the DDR bus width (UB_BUS_WIDTH_BITS).

  • Bridged into pipelined WB signaling used by the controller.

High-throughput capture / DMA (UC domain -> SYS domain -> DDR):

  • A UC-domain stream source generates DW-bit beats.

  • The source is either an internal ramp or packed design samples.

  • Stream crosses UC->SYS via AsyncFIFO.

  • zipdma_s2mm writes the stream into DDR through a shared crossbar.

Clock domains

  • “sys” : CPU, CSR bus, zipdma_s2mm, Wishbone fabric

  • “uc” : UberClock DSP / sample domain

  • “ub_4x” : DDR3 PHY clock

  • “ub_4x_dqs” : DDR3 PHY clock 90° shifted (DQS)

  • “idelay” : IDELAYCTRL reference clock

External inputs (from SoC)

  • cap_enable_uc : 1 = capture external design samples, 0 = use ramp

  • cap_beats_uc : number of DW-bit beats to write

  • cap_sample : the selected 12-bit sample (UC domain)

CSRs (SYS domain)

  • dma_req : strobe to start DMA write

  • dma_addr0/1 : 64-bit base address (packed from two 32-bit regs)

  • dma_inc : increment mode for DMA

  • dma_size : transfer size encoding (zipdma convention)

  • dma_busy/dma_err : status from zipdma

  • calib_done : DDR controller calibration complete

DEFAULT_SERDES_RATIO = 4
DEFAULT_CAP_BEATS = 256
DEFAULT_S2MM_FIFO_DEPTH = 256