<!– SPDX-FileCopyrightText: 2026 Ahmed Imamović SPDX-FileCopyrightText: 2026 Tarik Hamedović SPDX-License-Identifier: CC-BY-SA-4.0 –>
soc
This module contains the top-level SoC assembly and command-line build entry point.
uberclock_soc/soc.py
Top-level LiteX SoC assembly for the Alinx AX7203 platform.
- This module is the integration layer that ties together:
Clock/reset generation (100 MHz sys + exact 65 MHz uc + optional DDR clocks)
Optional standard LiteDRAM main RAM (LiteX SDRAM controller path)
Optional UberDDR3 side-memory (custom DDR3 controller + DMA/S2MM path)
Optional LiteEth Ethernet / Etherbone
Optional HDMI output (LiteX Video pipeline)
Optional UberClock DSP core (Verilog block in the uc clock domain)
- Design intent:
Keep the target wrapper script tiny (it should just call build_main()).
Keep most “feature wiring” here, while block internals live in their own files (clocking.py, ubddr3.py, uberclock_core.py, etc.).
- class uberclock_soc.soc.BaseSoC(*args: Any, **kwargs: Any)[source]
Bases:
SoCCoreAX7203 SoC with optional peripherals and optional UberClock/UberDDR3 blocks.
- Clock domains (via CRG):
sys : CPU/CSR domain, default 100 MHz
uc : UberClock domain, exact 65 MHz
ub_4x : DDR PHY clock (optional), 400 MHz
ub_4x_dqs: DDR DQS 90° clock (optional), 400 MHz @ +90°
idelay : IDELAYCTRL reference, 200 MHz
- Memory options:
Integrated LiteX main RAM (default 512 KiB)
Optional LiteDRAM (if integrated_main_ram_size == 0 AND not using UberDDR3)
Optional UberDDR3 as side memory mapped at 0xA0000000
- SYS_CLK_HZ_DEFAULT = 100000000.0
- INTEGRATED_MAIN_RAM_BYTES = 262144
- UBDDR3_BASE = 2684354560
- UBDDR3_SIZE = 268435456