<!– SPDX-FileCopyrightText: 2026 Ahmed Imamović SPDX-FileCopyrightText: 2026 Tarik Hamedović SPDX-License-Identifier: CC-BY-SA-4.0 –>

wishbone

This module provides the wishbone bridge and crossbar helpers used by the UberDDR3 integration.

class uberclock_soc.wishbone.ClassicToPipelinedWishboneBridge(*args: Any, **kwargs: Any)[source]

Bases: LiteXModule

Wraps the Verilog module wbc2pipeline.v to convert a classic Wishbone bus (LiteX-facing) into a pipelined Wishbone bus (UberDDR3-facing).

Interfaces:

  • self.s : classic Wishbone slave interface (connects to SoC bus).

  • m_* signals: pipelined Wishbone master raw signals (to downstream).

class uberclock_soc.wishbone.PipelinedWishboneXbar2M1S(*args: Any, **kwargs: Any)[source]

Bases: LiteXModule

Wraps the Verilog module wbxbar.v configured as:

  • NM = 2 masters

  • NS = 1 slave

Intended topology for UberDDR3:

  • Master 0: CPU access path (classic -> converter -> c2p bridge)

  • Master 1: DMA engine (zipdma_s2mm)

  • Slave 0: DDR3 controller (ddr3_top)