<!– SPDX-FileCopyrightText: 2026 Ahmed Imamović SPDX-FileCopyrightText: 2026 Tarik Hamedović SPDX-License-Identifier: CC-BY-SA-4.0 –>

clocking

This module defines the AX7203 clock/reset generation strategy used by the SoC.

class uberclock_soc.clocking.UberClockCRG(*args: Any, **kwargs: Any)[source]

Bases: LiteXModule

Clock/reset generation for the UberClock SoC on a 7-series FPGA (Artix-7).

CLKIN_HZ = 200000000.0

SYS_CLK_HZ = 100000000.0

UC_CLK_HZ = 65000000.0

DDR4X_CLK_HZ = 400000000.0

IDELAY_HZ = 200000000.0

MMCM_MARGIN = 1e-06

do_finalize()[source]: Force pll1 ratios to guarantee 65.000 MHz for the UberClock domain.