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CSR Map

This page summarizes the software-visible Control and Status Registers (CSRs) generated by LiteX for the uberClock SoC.

The CSR region is memory-mapped at:

0xF0000000

Within that region, LiteX exposes timer, DMA, datapath control, event, UART, and Ethernet-related register banks.

Overview

The most important CSR banks for the uberClock design are:

  • UBDDR3 for DDR3-backed DMA control

  • MAIN for DSP, routing, FIFO, and capture control

  • EVM for event/interrupt signaling

  • CFG_LINK for atomic configuration commit into the datapath

  • UART for firmware console I/O

The exact register names come from the auto-generated LiteX csr.h file.

UBDDR3 bank

Base address:

0xF0000800

This bank controls high-speed capture into DDR3.

DMA control registers

  • dma_req – start a DMA request

  • dma_inc – enable incrementing destination address

  • dma_size – transfer size encoding

  • dma_addr0 – low 32 bits of DDR destination address

  • dma_addr1 – high 32 bits of DDR destination address

DMA status registers

  • dma_busy – DMA transfer is active

  • dma_err – DMA error flag

  • calib_done – DDR3 controller initialization/calibration complete

This bank is used by the high-speed capture workflow and the UDP export flow.

MAIN bank

Base address:

0xF0001000

This is the main software-visible control surface for the DSP datapath.

NCO and phase control

  • phase_inc_nco

  • phase_inc_down_1 .. phase_inc_down_5

  • phase_inc_down_ref

  • phase_inc_cpu1 .. phase_inc_cpu5

These registers control the numerically controlled oscillator and the downconversion / CPU-generated phase increments used in the signal path.

Magnitude and gain control

  • nco_mag

  • mag_cpu1 .. mag_cpu5

  • gain1 .. gain5

These registers set the signal magnitudes and per-channel gains.

Routing and debug selection

  • input_select

  • upsampler_input_mux

  • output_select_ch1

  • output_select_ch2

  • lowspeed_dbg_select

  • highspeed_dbg_select

These registers control routing through the datapath and select which internal signals are exposed through the debug paths.

CPU-fed sample injection

  • upsampler_input_x

  • upsampler_input_y

  • final_shift

These registers allow firmware to inject low-rate samples into the datapath and adjust final output scaling.

FIFO interface

Downsample FIFO registers:

  • ds_fifo_pop

  • ds_fifo_x

  • ds_fifo_y

  • ds_fifo_overflow

  • ds_fifo_underflow

  • ds_fifo_clear

  • ds_fifo_flags

Upsampler FIFO registers:

  • ups_fifo_x

  • ups_fifo_y

  • ups_fifo_push

  • ups_fifo_overflow

  • ups_fifo_underflow

  • ups_fifo_clear

  • ups_fifo_flags

These registers provide the firmware-visible streaming interface used for low-speed interaction with the DSP path.

Low-speed capture

  • cap_enable

  • cap_beats

  • cap_arm

  • cap_idx

  • cap_done

  • cap_data

These registers support both the low-speed capture path and the control side of the DDR3-backed capture flow.

Readback / measurement

  • magnitude

  • phase

These registers expose processed measurement-style outputs back to firmware.

EVM bank

Base address:

0xF0001800

This bank provides the event manager used by the firmware runtime.

Registers:

  • status

  • pending

  • enable

The main event exposed here is ce_down, which is promoted into a LiteX interrupt/event source and used by firmware to service the low-rate runtime path.

CTRL bank

Base address:

0xF0002800

Registers:

  • reset

  • scratch

  • bus_errors

This bank provides generic SoC control and debug support.

UART bank

Base address:

0xF0005000

Registers include:

  • rxtx

  • txfull

  • rxempty

  • ev_status

  • ev_pending

  • ev_enable

  • txempty

  • rxfull

This bank underlies the firmware UART console.

Other generated banks

The generated CSR space also includes:

  • TIMER1 at 0xF0000000

  • ETHMAC at 0xF0003000

  • ETHPHY at 0xF0003800

  • IDENTIFIER_MEM at 0xF0004000

  • TIMER0 at 0xF0004800

These are part of the LiteX SoC environment but are less central to the uberClock-specific DSP control path.

Notes

The exact register names and helper accessors are generated by LiteX into generated/csr.h. Firmware code normally accesses them through the generated inline functions such as:

main_phase_inc_nco_write(value);
main_gain1_write(value);
main_cap_enable_write(1);
ubddr3_dma_req_write(1);

See also