Verilog IP
This section corresponds to 2.soc-litex/1.hw.
The directory contains the RTL modules instantiated by the CPU-controlled SoC. It is the hardware library that backs the LiteX-based top-level design.
This section corresponds to 2.soc-litex/1.hw.
The directory contains the RTL modules instantiated by the CPU-controlled SoC. It is the hardware library that backs the LiteX-based top-level design.