VProc and mem_model Co-simulation Components
This page summarizes 3.miniac/4.sim/models/cosim/README.md.
Overview
The VProc virtual processor and mem_model sparse memory model form the core of
the co-simulation environment for the Wireguard FPGA top-level test bench. The
soc_cpu.VProc instance runs user code against the simulated design, while
the memory model provides shared sparse memory that can be accessed from both
software and HDL.
VProc
VProc is a co-simulation component that allows a natively compiled user program to run against an HDL processor component. It exposes C and C++ APIs for bus transactions and for advancing simulation time.
The documented integration uses a local soc_if interface rather than a
standard interconnect such as AXI or Avalon. Multiple VProc instances can be
instantiated, each with its own node number.
The original README also references several architecture diagrams and API illustrations:
mem_model
The test bench also uses the mem_model co-simulation component. It provides a sparse C memory model together with HDL access components and a software API.
The API exposes read and write functions over shared address spaces and allows both HDL logic and multiple VProc instances to interact with the same memory.
The original README references additional diagrams:
Integration Notes
The directory contains HDL wrapper modules such as f_VProc.sv and
mem_model.sv plus the supporting Verilog headers and prebuilt host
libraries. For native simulation code:
Include
VProcClass.hfor the C++ VProc API orVUser.hfor the C API.Include
mem.hfor the memory model API.When compiling as C++, wrap the C headers in
extern "C".
Example:
extern "C" {
#include "VUser.h"
#include "mem.h"
}